Re: Bus Timing on the C64: Help
                                       
   From: John Iannetta <73510.2152@CompuServe.COM>
   Reply to: John Iannetta
   Date: Thu, 26 Nov 1998 02:31:09 -0500
   Organization: CompuServe, Inc. (1-800-689-0736)
   References:
          <73iblk$trb$1@nnrp1.dejanews.com>
    moshly@my-dejanews.com said,

"I'm trying to design an I/O chip (6522 style) using a Vantis MACH4-64/32, but
all the timing info I have does not seem to match the timing of my SX64.

I've measured the relationship between the dot clock and the phase 2 clock
signals and found that they appear to be delayed by half an 8Mhz dot clock
period (31.25 nano seconds).

Example: (measured from the cartridge port on a SX64). One character = 31.25ns

Dot             00110011001100110011001100110011001100110011001100
P2CLK           01111111111111111000000000000000011111111111111110

Is this normal ?".

    VIC, a 6567 (NTSC) or 6569 (PAL) generates phase 0 by dividing the dot
clock frequency (from the clock circuit) by eight.  The dot clock input pin of
VIC is tied to pin 6 of the cartridge port.  Phase 0 is inverted by the 6510
MPU to produce phase 2, which connects to pin E of the cartridge port.
Ideally, the edges of the dot clock and phase 2 should coincide.  But there are
propagation delays in VIC and in the MPU; the 6510 rise and fall time specs are
25 ns maximum.  Considering that NMOS techology is used, my feeling is that a
32 ns overall delay is quite normal.

    Ash also said,

"Also I wrote a simple loop, (1 poke $de00,1:goto 1) and measured the IO1 chip
select line and found that the PLA outputs 2 pulses per poke. Is this normal ?

Example: One character = 125ns

P2CLK   00001111000011110000111100001111

Can someone explain this, why 2 pulses ?".

    The first negative pulse is a read access; the second is a write access.
The BASIC POKE command uses INDIRECT INDEXED addressing.  The command winds up
doing a:

STA ($14),Y

with $00 in .Y, $00 in address $14, and $DE in $15.  The instruction takes six
clock cycles.  The first two fetch the opcode and operand.  The next two fetch
the low and high bytes of the address.  The MPU must then add .Y to that 16-bit
number, put it onto the address bus, and connect the .A register to the data
bus.  It can do that; a LDA ($14),Y takes only five cycles.  But for a STA, the
R/-W line must be taken low during the time that the phase 2 line is low; there
isn't enough time.  So the line goes low between the fifth and sixth cycles,
and the fifth cycle does an inadvertent read.

    Ash concluded,

"For normal interfacing, do I just wait half a P2CLK then qualify the address &
R/W, and then transfer the data on the falling edge of the P2CLK ?".

    Yes.  Make sure that you honor the setup and hold times of your SRAM,
EPROM, etc.

--
I pressed RETURN, and the message said, "Missing GOSUB".

                          John