Re: Best way to play samples on *both* 8580 and 6581
                                       
   From: John Iannetta <76703.4244@CompuServe.COM>
   Reply to: John Iannetta
   Date: Sat, 03 Oct 1998 03:27:35 -0400
   Organization: CompuServe, Inc. (1-800-689-0736)
   References:
          <slrn719lih.ff8.martijnb@mud.stack.nl>
    Nate Dannenberg said (about PDM or Pulse Duration Modulation, also called
Pulse Width Modulation):

"  Because each voice now only produces a 4-bit number, you only need a
   composite pulse that is at most, 16 microseconds in duration. Shown here
   is the maximum sample rate, 63 kHz, achievable with two voices using
   this method.  To maintain a reasonable volume level, one must pump each
   nybble through the upper four bits of the corresponding voice's pulse
   register (this also maintains an accurate sample resolution).".

    I don't think that you want to do that.  Let's assume that the system clock
frequency is exactly 1.024 MHz, and you are using voice 1 (for the high nybble
of your 8-bit data).  You could write 0 to register 0, and 128 to register 1;
that would give an oscillator frequency of 2 kHz (512 clock cycles).  If your
data are sampled at a 64 kHz rate, you would fetch a nybble every 16 clock
cycles, shift left three times, add it to a 16-bit counter, and write the sum
to registers 2 (low byte) and 3 (high byte).  Then, add 128 to your counter and
repeat the process.

    If you were to write each nybble to the duty-cycle registers, without
adding the increasing counter value, you would throw away 31 out of every 32
samles; your sampling rate would effectively be 2 kHz.  Each SID oscillator
uses a 12-bit counter that starts incrementing when bit 3 of register 4 is
cleared.  Selecting pulse waveform, the output voltage then goes low.  When
the SID counter value => the duty-cycle value, the output voltage goes high.
No matter how often you write the same number to the duty-cycle registers, the
voltage will stay low until the end of the 2 kHz period (512 clock cycles).
But by writing an ever-increasing number to the duty-cycle registers every 16
clock cycles, the SID counter value becomes less than the duty-cycle value, and
the voltage goes low.  Until the duty-cycle value is reached, when the voltage
goes high.  That happens 32 times each 2 kHz period, giving a 64 kHz frequency.

--
When backing up your hard drive, shift into reverse gear S M O O T H L Y.

                      John